Results
author = "GAIONI, Luigi"
A 3D Vertically Integrated Deep N-Well CMOS MAPS for the SuperB Layer0
Author(s) :
TRAVERSI, GIANLUCA
,
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RATTI, LODOVICO
,
RE, VALERIO
Description :
Deep N-Well (DNW) Monolithic Active Pixel Sensors (MAPS) have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hy- brid pixels systems. In these devices the triple well option, available in deep submicron processes, is exploited to impl...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
2D and 3D CMOS MAPS with high performance pixel-level signal processing
Author(s) :
TRAVERSI, GIANLUCA
,
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RATTI, LODOVICO
,
RE, VALERIO
Description :
Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep su...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
Analog front-end for monolithic and hybrid pixels in a vertical integration CMOS technology
Author(s) :
MANAZZA, ALESSIA
,
ZUCCA, STEFANO
,
GAIONI, LUIGI
,
RATTI, LODOVICO
,
TRAVERSI, GIANLUCA
Description :
This work is concerned with the design of two different analog channels for hybrid and monolithic pixels in view of applications to the vertex detector at the SuperB Factory. The circuits have been designed in a 130 nm CMOS, vertical integration technology, which may provide some advantages in terms...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors
Author(s) :
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RATTI, LODOVICO
,
TRAVERSI, GIANLUCA
,
RE, VALERIO
Description :
In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric material...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
TID-Induced Degradation in Static and Noise Behavior of Sub-100 nm Multifinger Bulk NMOSFETs
Author(s) :
RATTI, LODOVICO
,
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RE, VALERIO
,
TRAVERSI, GIANLUCA
Description :
This paper is concerned with the study of the total ionizing dose (TID) effects in NMOS transistors belonging to 90 and 65 nm CMOS technologies from different manufacturers. Results from static and noise measurements are used to collect further evidence for a static and noise degradation model invol...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
The Apsel65 front-end chip for the readout of pixel sensors in the 65 nm CMOS node
Author(s) :
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RATTI, LODOVICO
,
RE, VALERIO
,
TRAVERSI, GIANLUCA
Description :
This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65 nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work will present a summary of the ...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
Analog design criteria for high-granularity detector readout in the 65 nm CMOS technology
Author(s) :
MANGHISONI, MASSIMO
,
GAIONI, LUIGI
,
RATTI, LODOVICO
,
RE, VALERIO
,
TRAVERSI, GIANLUCA
Description :
This work is concerned with the study of the analog properties, in particular in terms of gain and noise performance, of MOSFET devices belonging to a 65 nm CMOS technology. Silicon vertex detectors at the next generation colliders will be read out by means of front-end electronics based on fabricat...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging
Author(s) :
RATTI, LODOVICO
,
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RE, VALERIO
,
TRAVERSI, GIANLUCA
Description :
Three-dimensional monolithic pixel sensors have been designed following the same approach that was exploited for the development of the so-called deep N-well (DNW) MAPS in planar CMOS process. The new 3D design relies upon stacking two homogeneous layers fabricated in a 130 nm CMOS technology. One o...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
Fast Analog Front-end for the Readout of the SuperB SVT Inner Layers
Author(s) :
TRAVERSI, GIANLUCA
,
RE, VALERIO
,
MANGHISONI, MASSIMO
,
GAIONI, LUIGI
,
RATTI, LODOVICO
Description :
The SuperB factory is an Italian e+ e- acceler- ator project that plans to reach a luminosity higher than 10^36 cm−2s−1 by means of a very small beam size and with moderate beam currents. To achieve the performance imposed by physics, six layers of microstrip silicon sensors, with different pitches ...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English
A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics
Author(s) :
GAIONI, LUIGI
,
MANGHISONI, MASSIMO
,
RATTI, LODOVICO
,
RE, VALERIO
,
TRAVERSI, GIANLUCA
Description :
This work is concerned with the design criteria and the experimental characterization of front-end electronics in a 65-nm CMOS technology for the readout of hybrid pixels and of monolithic active pixel sensors using a deep N-well as their collecting electrode. The work presents a summary of the expe...
Repository :
Aisberg - Archivio Istituzionale Università di Bergamo
Language(s) :
English