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Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors

Description : The large scale of integration provided by CMOS processes with minimum feature size in the 100 nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, proce...
Language(s) : English
Subject(s) : CMOS; microelectronics; scaling; sensors; , Electrical & Electronics Engineering , Ingegneria industriale e dell'informazione
Publisher(s) : Elsevier Science Limited
Contributor(s) :
Source(s) :
Publication Date(s) : 2010-01-01